Many engineers in electronics design and manufacturing are familiar with JTAG boundary scan as a method for in-circuit debugging and programming devices. The IEEE Std. 1149.1 has been around for a quarter of a century now, in electronics terms that is several lifetimes! However the advent of BGA packaging presented the industry with a new challenge – how to access and test those connections. Traditional bed-of-nails or flying probe machines have restricted access.
This is where boundary scan comes into its own. When boundary scan cells are in test mode they can be used to control the values being driven from an enabled device onto a net and also be used to monitor the value of that net. This means that by driving one pin and monitoring others a JTAG connection test can detect opens, shorts, missing pull resistors and ‘stuck-at’ faults – even on inaccessible BGA connections.
JTAG boundary scan is implemented on many ICs so from the very start of a design it is possible to analyse test coverage, thus improving Design for Test, speeding up prototype debug, and creating manufacturing tests.
XJTAG, a leading supplier of IEEE Std. 1149.x compliant boundary scan tools, has written an introduction to JTAG that introduces the reader to how JTAG / boundary scan is used to test a board. The free paper, “What is JTAG?”, can be downloaded from the XJTAG website.